1. Field of the Invention
The present invention relates to computer chip architectures, and more particularly to an on-chip data transfer network that includes a scalable mesh architecture with re-configurable paths, which incorporates a configuration manager, for improved information routing between multiple on-chip modules.
2. Description of the Related Art
Computer systems have traditionally comprised a system unit or housing which comprises a plurality of electrical components comprising the computer system. A computer system typically includes a motherboard, which is configured to hold the microprocessor and memory, and the one or more busses used in the computer system. The motherboard typically comprises a plurality of computer chips or electrical components including intelligent peripheral devices, bus controllers, processors, bus bridges, etc.
More recently, computer systems are evolving toward an integration of functions into a handful of computer chips. This coincides with the ability of chip makers to place an increasingly large number of transistors on a single chip. For example, currently chip manufacturers are able to place up to ten million transistors on a single integrated circuit or monolithic substrate. It is anticipated that within several years chip makers will be able to place one billion transistors on a single chip. Thus, computer systems are involving toward comprising a handful of computer chips, where each computer chip comprises a plurality of functions. The integration of a plurality of modules or functions on a single computer chip requires an improved data transfer chip architecture. Also, due to the shorter distances and tighter integration of components on a chip, new data transfer architectures are necessary to take advantage of this environment. Therefore, an improved system and method is desired for including a plurality of different functions or modules on a single computer chip while providing efficient data transfers.